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ISLPED
1999
ACM
100views Hardware» more  ISLPED 1999»
15 years 11 months ago
Selective instruction compression for memory energy reduction in embedded systems
We propose a technique for reducing the energy required by rmware code to execute on embedded systems. The method is based on the idea of compressing the most commonly executed in...
Luca Benini, Alberto Macii, Enrico Macii, Massimo ...
ISCA
1998
IEEE
128views Hardware» more  ISCA 1998»
15 years 11 months ago
Analytic Evaluation of Shared-memory Systems with ILP Processors
This paper develops and validates an analytical model for evaluating various types of architectural alternatives for shared-memory systems with processors that aggressively exploi...
Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mar...
174
Voted
WSC
1997
15 years 8 months ago
Execution-Driven Simulators for Parallel Systems Design
Evaluating, analyzing and predicting the performance of a parallel system is challenging due to the complex inter-play between the application characteristics and architectural fe...
Anand Sivasubramaniam
DATE
2009
IEEE
138views Hardware» more  DATE 2009»
16 years 1 months ago
Hardware/software co-design architecture for thermal management of chip multiprocessors
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
Omer Khan, Sandip Kundu
ACISICIS
2008
IEEE
16 years 1 months ago
SIMPA: A SIP-Based Mobile Payment Architecture
In recent years, many Mobile Payment (MP) schemes have been proposed and used in practise. However, a prerequisite for extended acceptance and adoption of MP technologies is to de...
Ge Zhang, Feng Cheng 0002, Christoph Meinel