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JPDC
2000
141views more  JPDC 2000»
15 years 6 months ago
A System for Evaluating Performance and Cost of SIMD Array Designs
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
Martin C. Herbordt, Jade Cravy, Renoy Sam, Owais K...
TPDS
2002
134views more  TPDS 2002»
15 years 6 months ago
Performance of CORBA-Based Client-Server Architectures
Middleware has been introduced to provide interoperability as well as transparent location of servers in heterogeneous client-server environments. Although such benefits accrue fro...
Istabrak Abdul-Fatah, Shikharesh Majumdar
SIGCOMM
2009
ACM
16 years 1 months ago
Optimizing the BSD routing system for parallel processing
The routing architecture of the original 4.4BSD [3] kernel has been deployed successfully without major design modification for over 15 years. In the unified routing architectur...
Qing Li, Kip Macy
ET
2002
115views more  ET 2002»
15 years 6 months ago
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
ICCAD
2002
IEEE
141views Hardware» more  ICCAD 2002»
16 years 3 months ago
A hierarchical modeling framework for on-chip communication architectures
— The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication archite...
Xinping Zhu, Sharad Malik