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ICPP
2009
IEEE
16 years 1 months ago
Speeding Up Distributed MapReduce Applications Using Hardware Accelerators
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
Yolanda Becerra, Vicenç Beltran, David Carr...
ICPPW
2009
IEEE
16 years 1 months ago
Multiprocessor Synchronization and Hierarchical Scheduling
Multi-core architectures have received significant interest as thermal and power consumption problems limit further increase of speed in single-cores. In the multi-core research ...
Farhang Nemati, Moris Behnam, Thomas Nolte
IISWC
2009
IEEE
16 years 1 months ago
SD-VBS: The San Diego Vision Benchmark Suite
—In the era of multi-core, computer vision has emerged as an exciting application area which promises to continue to drive the demand for both more powerful and more energy effi...
Sravanthi Kota Venkata, Ikkjin Ahn, Donghwan Jeon,...
MICRO
2009
IEEE
132views Hardware» more  MICRO 2009»
16 years 1 months ago
EazyHTM: eager-lazy hardware transactional memory
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulka...
CIKM
2009
Springer
16 years 28 days ago
On the feasibility of multi-site web search engines
Web search engines are often implemented as centralized systems. Designing and implementing a Web search engine in a distributed environment is a challenging engineering task that...
Ricardo A. Baeza-Yates, Aristides Gionis, Flavio J...
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