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DSN
2007
IEEE
16 years 1 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
DSN
2007
IEEE
16 years 1 months ago
Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays
Programmable logic arrays (PLA), which can implement arbitrary logic functions in a two-level logic form, are promising as platforms for nanoelectronic logic due to their highly r...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
ESCIENCE
2007
IEEE
16 years 1 months ago
Tracing Resource Usage over Heterogeneous Grid Platforms: A Prototype RUS Interface for DGAS
Tracing resource usage by Grid users is of utmost importance — especially in the context of large-scale scientific collaborations such as within the High Energy Physics (HEP) c...
Rosario M. Piro, Michele Pace, Antonia Ghiselli, A...
FDL
2007
IEEE
16 years 1 months ago
Modelling Alternatives for Cycle Approximate Bus TLMs
Transaction level models (TLMs) can be constructed at t levels of abstraction, denoted as untimed (UT), cycle-approximate (CX), and cycle accurate (CA) in this paper. The choice o...
Martin Radetzki, Rauf Salimi Khaligh
GLOBECOM
2007
IEEE
16 years 1 months ago
Stability Emphasizing Cross-Layer Optimization of Transmit Power Allocation in Distributed Wireless Networks
Abstract— This paper theoretically analyzes cross-layer optimized design of transmit power allocation in distributed interference-limited wireless networks with asynchronously ac...
Stepán Kucera, Sonia Aïssa, Susumu Yos...
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