In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the obser...
Traditionally, rectilinear Steiner minimum trees (RSMT) are widely used for routing estimation in design optimizations like floorplanning and physical synthesis. Since it optimize...
Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sz...
Deploying multiple supply voltages (multi-Vdds) on one chip is an important technique to reduce dynamic power consumption. In this work we present an optimality study for resource...
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
With ever-increasing power density and cooling costs in modern high-performance systems, dynamic thermal management (DTM) has emerged as an effective technique for guaranteeing th...
Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K....