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ISQED
2006
IEEE
101views Hardware» more  ISQED 2006»
16 years 26 days ago
Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance...
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Oz...
TRIDENTCOM
2006
IEEE
16 years 25 days ago
Cross-layer multi-hop wireless routing for inter-vehicle communication
— Ad-hoc networking provides a cost-effective support structure for inter-vehicle communication. A decentralized peerto-peer information dissemination architecture is well suited...
Jatinder Pal Singh, Nicholas Bambos, Bhaskar Srini...
ICPPW
2005
IEEE
16 years 13 days ago
A Practical Approach to the Rating of Barrier Algorithms Using the LogP Model and Open MPI
Large–scale parallel applications performing global synchronization may spend a significant amount of execution time waiting for the completion of a barrier operation. Conseque...
Torsten Hoefler, Lavinio Cerquetti, Torsten Mehlan...
ICWE
2003
Springer
16 years 1 days ago
Morphoanalysis of Spanish Texts: Two Applications for Web Pages
The applications described here follow up the works performed in the recent last years by the Data Structures and Computational Linguistics Group at Las Palmas de Gran Canaria Univ...
Octavio Santana Suárez, Zenón Jos&ea...
FPL
2009
Springer
135views Hardware» more  FPL 2009»
15 years 11 months ago
Fast critical sections via thread scheduling for FPGA-based multithreaded processors
As FPGA-based systems including soft processors become increasingly common, we are motivated to better understand the architectural trade-offs and improve the efficiency of these...
Martin Labrecque, J. Gregory Steffan