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ASPDAC
2010
ACM
163views Hardware» more  ASPDAC 2010»
15 years 4 months ago
A3MAP: architecture-aware analytic mapping for networks-on-chip
- In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) ...
Wooyoung Jang, David Z. Pan
HIPC
2009
Springer
15 years 4 months ago
Three scalable approaches to improving many-core throughput for a given peak power budget
Recently proposed techniques for peak power management [18] involve centralized decisionmaking and assume quick evaluation of the various power management states. These techniques...
John Sartori, Rakesh Kumar
ICRA
2009
IEEE
116views Robotics» more  ICRA 2009»
15 years 4 months ago
Kinematic analysis and optimal design of a 3T1R type parallel mechanism
In previous studies on 4-DOF parallel mechanisms with four sub-chains, only symmetric arrangement of those four chains connected to the top plate was considered. Such symmetric sha...
Sung Mok Kim, Whee Kuk Kim, Byung-Ju Yi
IJHPCA
2010
111views more  IJHPCA 2010»
15 years 4 months ago
Understanding Application Performance via Micro-benchmarks on Three Large Supercomputers: Intrepid, Ranger and Jaguar
Emergence of new parallel architectures presents new challenges for application developers. Supercomputers vary in processor speed, network topology, interconnect communication ch...
Abhinav Bhatele, Lukasz Wesolowski, Eric J. Bohm, ...
DAC
2009
ACM
16 years 7 months ago
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo