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IWANN
2007
Springer
16 years 23 days ago
Interconnecting VLSI Spiking Neural Networks Using Isochronous Connections
This paper presents a network architecture to interconnect mixed-signal VLSI1 integrate-and-fire neural networks in a way that the timing of the neural network data is preserved. ...
Stefan Philipp, Andreas Grübl, Karlheinz Meie...
GLOBECOM
2006
IEEE
16 years 21 days ago
Multicast Support for a Storage Area Network Switch
— Efficient support of multicast traffic in Storage Area Networks (SANs) enables applications such as remote data replication and distributed multimedia systems, in which a ser...
Andrea Bianco, Paolo Giaccone, Enrico Maria Giraud...
IPPS
2006
IEEE
16 years 20 days ago
Exploiting unbalanced thread scheduling for energy and performance on a CMP of SMT processors
This paper explores thread scheduling on an increasingly popular architecture: chip multiprocessors with simultaneous multithreading cores. Conventional multiprocessor scheduling,...
M. De Vuyst, Rakesh Kumar, Dean M. Tullsen
DATE
2005
IEEE
168views Hardware» more  DATE 2005»
16 years 8 days ago
Hardware Acceleration of Hidden Markov Model Decoding for Person Detection
This paper explores methods for hardware acceleration of Hidden Markov Model (HMM) decoding for the detection of persons in still images. Our architecture exploits the inherent st...
Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
ICMCS
2005
IEEE
132views Multimedia» more  ICMCS 2005»
16 years 7 days ago
A Two-Level CBIR Platform with Application to Brain MRI Retrieval
This paper presents a novel platform for image retrieval based on a two-level architecture inspired from human cognitive mechanisms. These two levels provide both generic similari...
John Moustakas, Kostas Marias, Socrates Dimitriadi...