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ICIP
2005
IEEE
16 years 8 months ago
High throughput 2D DCT/IDCT processor for video coding
This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with high throughput, reduced hardware, and a parallel-pipeline scheme. This architecture allows the process...
Gustavo A. Ruiz, Juan A. Michell, Angel M. Buron
ARITH
2009
IEEE
16 years 1 months ago
Datapath Synthesis for Standard-Cell Design
Datapath synthesis for standard-cell design goes through extraction of arithmetic operations from RTL code, high-level arithmetic optimizations and netlist generation. Numerous ar...
Reto Zimmermann
WEBI
2009
Springer
16 years 1 months ago
An Empirical Study on Maximum Latency Saving in Web Prefetching
—This paper presents an empirical study to investigate the maximum benefits that web users can expect from prefetching techniques in the current web. To this end a perfect web p...
B. de la Ossa, Julio Sahuquillo, Ana Pont, Jos&eac...
ARGMAS
2009
Springer
16 years 1 months ago
Realizing Argumentation in Multi-agent Systems Using Defeasible Logic Programming
We describe a working multi-agent architecture based on Defeasible Logic Programming (DeLP) by Garc´ıa and Simari where agents are engaged in an argumentation to reach a common c...
Matthias Thimm
IOLTS
2006
IEEE
81views Hardware» more  IOLTS 2006»
16 years 20 days ago
Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers
This work intends to evaluate the effect of a Single Event Upsets (SEUs) and crosstalk faults in a NoC router architecture by developing a fault injection mechanism, allowing an a...
Arthur Pereira Frantz, Luigi Carro, Érika F...