This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with high throughput, reduced hardware, and a parallel-pipeline scheme. This architecture allows the process...
Datapath synthesis for standard-cell design goes through extraction of arithmetic operations from RTL code, high-level arithmetic optimizations and netlist generation. Numerous ar...
—This paper presents an empirical study to investigate the maximum benefits that web users can expect from prefetching techniques in the current web. To this end a perfect web p...
B. de la Ossa, Julio Sahuquillo, Ana Pont, Jos&eac...
We describe a working multi-agent architecture based on Defeasible Logic Programming (DeLP) by Garc´ıa and Simari where agents are engaged in an argumentation to reach a common c...
This work intends to evaluate the effect of a Single Event Upsets (SEUs) and crosstalk faults in a NoC router architecture by developing a fault injection mechanism, allowing an a...