3922 search results - page 188 / 785 » The IA-64 Architecture at Work |
262
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CVPR
2012
IEEE
13 years 9 months ago
2012
IEEE
Many architectural scenes contain symmetric or repeated structures, which can generate erroneous image correspondences during structure from motion (Sfm) computation. Prior work h...
179
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DAC
2012
ACM
13 years 9 months ago
2012
ACM
In this work, we propose a fast and accurate chip/package thermomechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also present a design optimization meth...
181
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DAC
2012
ACM
13 years 9 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
163
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DAC
2012
ACM
13 years 9 months ago
2012
ACM
Due to the large geometry of through-silicon-vias (TSVs) and their connections to the power grid, significant current crowding can occur in 3D ICs. Prior works model TSVs and pow...
421
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DAC
2012
ACM
13 years 9 months ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...