3922 search results - page 157 / 785 » The IA-64 Architecture at Work |
172
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ISCA
2009
IEEE
16 years 1 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
167
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ISCA
2009
IEEE
16 years 1 months ago
2009
IEEE
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
205
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EMSOFT
2007
Springer
16 years 22 days ago
2007
Springer
We address the problem of mapping a set of processes which communicate synchronously on a distributed platform. The Time Triggered Architecture (TTA) proposed by Kopetz for the co...
186
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IEEEPACT
2005
IEEE
16 years 5 days ago
2005
IEEE
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
170
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SIGCOMM
2004
ACM
15 years 12 months ago
2004
ACM
Currently the Internet has only one level of name resolution, DNS, which converts user-level domain names into IP addresses. In this paper we borrow liberally from the literature ...