Sciweavers

3922 search results - page 150 / 785
» The IA-64 Architecture at Work
Sort
View
CODES
2004
IEEE
15 years 10 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
IPPS
2007
IEEE
16 years 26 days ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
CSCW
2006
ACM
16 years 16 days ago
Response times in N-user replicated, centralized, and proximity-based hybrid collaboration architectures
We evaluate response times, in N-user collaborations, of the popular centralized (client-server) and replicated (peer-to-peer) architectures, and a hybrid architecture in which ea...
Sasa Junuzovic, Prasun Dewan
BIRTHDAY
2010
Springer
15 years 5 months ago
The Architecture Description Language MoDeL
m, modules, types and operations), different kinds of abstractions (functional/data, types/objects etc.) without falling into a loose collection of diagram languages. Considering a...
Peter Klein
ICCAD
2002
IEEE
141views Hardware» more  ICCAD 2002»
16 years 3 months ago
A hierarchical modeling framework for on-chip communication architectures
— The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication archite...
Xinping Zhu, Sharad Malik