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CISIS
2010
IEEE
15 years 12 months ago
Study of Variations of Native Program Execution Times on Multi-Core Architectures
Abstract—Program performance optimisations, feedbackdirected iterative compilation and auto-tuning systems [1] all assume a fixed estimation of execution time given a fixed inp...
Abdelhafid Mazouz, Sid Ahmed Ali Touati, Denis Bar...
ISVLSI
2002
IEEE
104views VLSI» more  ISVLSI 2002»
15 years 11 months ago
Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse Computation
Modular inverse computation is needed in several public key cryptographic applications. In this work, we present two VLSI hardware implementations used in the calculation of Montg...
Adnan Abdul-Aziz Gutub, Alexandre F. Tenca, &Ccedi...
IPPS
2000
IEEE
15 years 11 months ago
Augmenting Modern Superscalar Architectures with Configurable Extended Instructions
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...
Xianfeng Zhou, Margaret Martonosi
ISCA
1998
IEEE
144views Hardware» more  ISCA 1998»
15 years 10 months ago
Declustered Disk Array Architectures with Optimal and Near-Optimal Parallelism
This paper investigates the placement of data and parity on redundant disk arrays. Declustered organizations have been traditionally used to achieve fast reconstruction of a faile...
Guillermo A. Alvarez, Walter A. Burkhard, Larry J....
ISCA
1997
IEEE
113views Hardware» more  ISCA 1997»
15 years 10 months ago
Effects of Communication Latency, Overhead, and Bandwidth in a Cluster Architecture
This work provides a systematic study of the impact of communication performance on parallelapplications in a high performance network of workstations. We develop an experimental ...
Richard P. Martin, Amin Vahdat, David E. Culler, T...