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IJNSEC
2008
106views more  IJNSEC 2008»
15 years 6 months ago
Parallel Hardware Architectures for the Cryptographic Tate Pairing
Identity-based cryptography uses pairing functions,which are sophisticated bilinear maps defined on elliptic curves.Computing pairings efficiently in software is presently a relev...
Guido Marco Bertoni, Luca Breveglieri, Pasqualina ...
JSS
2006
104views more  JSS 2006»
15 years 6 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
Jacob Engel, Daniel Lacks, Taskin Koçak
TIFS
2008
142views more  TIFS 2008»
15 years 6 months ago
An FPGA-Based Network Intrusion Detection Architecture
Abstract--Network intrusion detection systems (NIDSs) monitor network traffic for suspicious activity and alert the system or network administrator. With the onset of gigabit netwo...
Abhishek Das, David Nguyen, Joseph Zambreno, Gokha...
VLSISP
2008
129views more  VLSISP 2008»
15 years 6 months ago
Architecture and Evaluation of an Asynchronous Array of Simple Processors
Abstract-- This paper presents the architecture of an Asynchronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and en...
Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, O...
DEBU
2000
118views more  DEBU 2000»
15 years 6 months ago
A Dynamic Query Processing Architecture for Data Integration Systems
Execution plans produced by traditional query optimizers for data integration queries may yield poor performance for several reasons. The cost estimates may be inaccurate, the mem...
Luc Bouganim, Françoise Fabret, C. Mohan, P...