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DAC
2006
ACM
16 years 7 months ago
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil...
HPCA
2006
IEEE
16 years 7 months ago
An approach for implementing efficient superscalar CISC processors
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...
ICCAD
2001
IEEE
91views Hardware» more  ICCAD 2001»
16 years 3 months ago
A System for Synthesizing Optimized FPGA Hardware from MATLAB
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
Malay Haldar, Anshuman Nayak, Alok N. Choudhary, P...
IROS
2009
IEEE
162views Robotics» more  IROS 2009»
16 years 1 months ago
Novel mechanical design of biped robot SHERPA using 2 DOF cable differential modular joints
— This paper discusses the mechanical kinematics solutions and design aspects of the biped robot SHERPA, a bipedal platform able to walk and carry load. Starting from the analysi...
Ionut Mihai Constantin Olaru, Sébastien Kru...
ISCA
2007
IEEE
162views Hardware» more  ISCA 2007»
16 years 27 days ago
BulkSC: bulk enforcement of sequential consistency
While Sequential Consistency (SC) is the most intuitive memory consistency model and the one most programmers likely assume, current multiprocessors do not support it. Instead, th...
Luis Ceze, James Tuck, Pablo Montesinos, Josep Tor...