2424 search results - page 319 / 485 » The High Level Architecture for Simulations |
140
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ISCAS
1999
IEEE
15 years 11 months ago
1999
IEEE
A general high-Q biquad lter architecture capable of operating in the GHz range is proposed and analyzed. This lter, which is usable in bandpass and lowpass applications, utilizes...
151
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INFOCOM
1998
IEEE
15 years 11 months ago
1998
IEEE
Reliable sender-based one-to-many protocols do not scale well due mainly to implosion caused by excessive rate of feedback packets arriving from receivers. We show that this probl...
184
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BIBE
2007
IEEE
15 years 8 months ago
2007
IEEE
In this paper we describe our design and characterization of a co-processor architecture to accelerate median-based phylogenetic reconstruction for generearrangement data. Our curr...
178
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CDC
2009
IEEE
15 years 7 months ago
2009
IEEE
In this paper, a new control approach for real time speed synchronization of multiple induction motors during speed acceleration and load changes is developed. The control strategy...
167
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CORR
2008
Springer
15 years 6 months ago
2008
Springer
This paper presents a brief overview of several studies concerning the indoor wireless communications at 60 GHz performed by the IETR. The characterization and the modeling of the...