2424 search results - page 313 / 485 » The High Level Architecture for Simulations |
181
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DAC
2004
ACM
16 years 7 months ago
2004
ACM
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
199
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is const...
208
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CODES
2003
IEEE
15 years 12 months ago
2003
IEEE
We present an approach to the automatic derivation of executable Process Network specifications from Weakly Dynamic Applications. We introduce the notions of Dynamic Single Assig...
159
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SACMAT
2003
ACM
15 years 12 months ago
2003
ACM
Traditional network security technologies such as firewalls and intrusion detection systems usually work according to a static ruleset only. We believe that a better approach to ...
145
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INFOCOM
1992
IEEE
15 years 10 months ago
1992
IEEE
The current Internet is based on a stateless (datagram) architecture. However, many recent proposals rely on the maintenance of state information within network routers, leading t...