2424 search results - page 312 / 485 » The High Level Architecture for Simulations |
157
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DAC
1997
ACM
15 years 10 months ago
1997
ACM
In this paper, we present a new hypergraph partitioning algorithm that is based on the multilevel paradigm. In the multilevel paradigm, a sequence of successively coarser hypergra...
174
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DAC
2004
ACM
15 years 10 months ago
2004
ACM
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickne...
174
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ASPDAC
2005
ACM
15 years 8 months ago
2005
ACM
Abstract— This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpos...
167
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LCN
2003
IEEE
15 years 12 months ago
2003
IEEE
Assuring guaranteed services and providing fair bandwidth sharing are much sought characteristics in the current network architecture research. The IntServ approaches achieve thos...
168
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ISSS
2002
IEEE
15 years 11 months ago
2002
IEEE
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...