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» The High Level Architecture for Simulations
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TPDS
2002
105views more  TPDS 2002»
15 years 6 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
200
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IJACTAICIT
2010
176views more  IJACTAICIT 2010»
15 years 3 months ago
A Secured Web Services Based E-Commerce Model for SMME Using Digital Identity
This paper deals with redesigning the existing e-commerce architecture that has provided a platform for the large companies to sell their products so that it can provide a place o...
Ashwin B. K., Kumaran K., Madhu Vishwanatham V., M...
DAC
2011
ACM
14 years 6 months ago
Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers
A three-dimensional (3D) CMOS imager constructed from stacking a pixel array of image sensors, an analog-to-digital converter (ADC) array, and an image signal processor (ISP) arra...
Hsiu-Ming Chang, Kwang-Ting (Tim) Cheng
DAC
2004
ACM
16 years 7 months ago
An integrated hardware/software approach for run-time scratchpad management
An ever increasing number of dynamic interactive applications are implemented on portable consumer electronics. Designers depend largely on operating systems to map these applicat...
Francesco Poletti, Paul Marchal, David Atienza, Lu...
EDOC
2008
IEEE
16 years 1 months ago
MDD4SOA: Model-Driven Service Orchestration
Service-Oriented Architectures (SOAs) have become an important cornerstone of the development of enterprise-scale software applications. Although a range of domain-specific langua...
Philip Mayer, Andreas Schroeder, Nora Koch