2424 search results - page 300 / 485 » The High Level Architecture for Simulations |
157
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DFT
2003
IEEE
15 years 12 months ago
2003
IEEE
This paper proposes a new fault model and its modeling and analysis methods in a clockless asynchronous wave pipeline for extensive yield evaluation and assurance. It is highly de...
157
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ISCAS
2003
IEEE
15 years 12 months ago
2003
IEEE
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
151
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
In this paper, we present an efficient methodology to validate high performance algorithms and prototype them using reconfigurable hardware. We follow a strict topdown Hardware/So...
169
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DATE
2000
IEEE
15 years 11 months ago
2000
IEEE
The composite signal flow model of computation targets systems with significant control and data processing parts. It builds on the data flow and synchronous data flow models ...
196
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CCL
1994
Springer
15 years 10 months ago
1994
Springer
Abstract: This paper describes the application of CLP (constraint logic programming) to several digital circuit design problems. It is shown that logic programming together with ef...