2424 search results - page 296 / 485 » The High Level Architecture for Simulations |
184
click to vote
BMCBI
2007
15 years 6 months ago
2007
Background: When conducting multiple hypothesis tests, it is important to control the number of false positives, or the False Discovery Rate (FDR). However, there is a tradeoff be...
210
click to vote
INFOCOM
2008
IEEE
16 years 1 months ago
2008
IEEE
— Load factor based congestion control schemes have shown to enhance network performance, in terms of utilization, packet loss and delay. In these schemes, using more accurate re...
161
click to vote
IEEEINTERACT
2002
IEEE
15 years 11 months ago
2002
IEEE
Smaller input data sets such as the test and the train input sets are commonly used in simulation to estimate the impact of architecture/micro-architecture features on the perform...
166
click to vote
MICRO
2008
IEEE
16 years 1 months ago
2008
IEEE
Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leadin...
162
click to vote
ICIP
2007
IEEE
16 years 8 months ago
2007
IEEE
Discrete tomography (DT) is concerned with the tomographic reconstruction of images that consist of only a small number of gray levels. DT reconstruction problems are usually unde...