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» The High Level Architecture for Simulations
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HPDC
1998
IEEE
15 years 11 months ago
Application Experiences with the Globus Toolkit
The development of applications and tools for highperformance "computational grids" is complicated by the heterogeneity and frequently dynamic behavior of the underlying...
Sharon Brunett, Karl Czajkowski, Steven Fitzgerald...
ENTCS
2002
92views more  ENTCS 2002»
15 years 6 months ago
PLCTools: Graph Transformation Meets PLC Design
This paper presents PLCTools, a formal environment for designing and simulating programmable controllers. Control models are specified with IEC FBD (Function Block Diagram), and t...
Luciano Baresi, Marco Mauri, Mauro Pezzè
DAC
2008
ACM
16 years 7 months ago
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high throughput and...
Aydin O. Balkan, Gang Qu, Uzi Vishkin
162
Voted
ANCS
2007
ACM
15 years 10 months ago
Experimental evaluation of a coarse-grained switch scheduler
Modern high performance routers rely on sophisticated interconnection networks to meet ever increasing demands on capacity. Previous studies have used a combination of analysis an...
Charlie Wiseman, Jonathan S. Turner, Ken Wong, Bra...
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
16 years 7 months ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...