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» The High Level Architecture for Simulations
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DAC
2002
ACM
16 years 7 months ago
IP delivery for FPGAs using Applets and JHDL
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
Michael J. Wirthlin, Brian McMurtrey
ANSS
2006
IEEE
16 years 20 days ago
Performance Enhancement by Eliminating Redundant Function Execution
Programs often call the same function with the same arguments, yielding the same results. We call this phenomenon, “function reuse”. Previously, we have shown such a behavior ...
Peng Chen, Krishna M. Kavi, Robert Akl
ISLPED
1999
ACM
143views Hardware» more  ISLPED 1999»
15 years 11 months ago
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
Kanad Ghose, Milind B. Kamble
SIGGRAPH
1996
ACM
15 years 10 months ago
Visual Models of Plants Interacting with Their Environment
Interaction with the environment is a key factor affecting the development of plants and plant ecosystems. In this paper we introduce a modeling framework that makes it possible t...
Radomír Mech, Przemyslaw Prusinkiewicz
IADIS
2004
15 years 8 months ago
GENESYS: Inovative Framework for Comprehensive Supervision in Multiple Domains
GeneSyS is an IST project (IST-2001-34162) developing a new generic middleware for supervising distributed systems at different levels such as Application, Network, System. The pr...
Balázs Pataki, Andrey Sadovykh, Stefan Wesn...