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» The High Level Architecture for Simulations
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VLSID
2002
IEEE
160views VLSI» more  VLSID 2002»
16 years 7 months ago
PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis
Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming...
A. B. Bhattacharyya, Shrutin Ulman
DAC
1994
ACM
15 years 10 months ago
Acyclic Multi-Way Partitioning of Boolean Networks
Acyclic partitioning on combinational boolean networks has wide range of applications, from multiple FPGA chip partitioning to parallel circuit simulation. In this paper, we prese...
Jason Cong, Zheng Li, Rajive Bagrodia
160
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SIPS
2007
IEEE
16 years 26 days ago
Multilevel Linc System Design for Power Efficiency Enhancement
Linear amplifier with nonlinear components (LINC) is a power amplifier (PA) linearization technique which offers both high PA efficiency and high linearity of wireless transmitter...
Kai-Yuan Jheng, Yuan-Jyue Chen, An-Yeu Wu
RSP
2005
IEEE
207views Control Systems» more  RSP 2005»
16 years 5 days ago
Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design
Embedded signal processing systems are usually associated with real-time constraints and/or high data rates so that fully software implementation are often not satisfactory. In th...
Sylvain Huet, Emmanuel Casseau, Olivier Pasquier
ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
16 years 5 days ago
Energy reduction in multiprocessor systems using transactional memory
The emphasis in microprocessor design has shifted from high performance, to a combination of high performance and low power. Until recently, this trend was mostly true for uniproc...
Tali Moreshet, R. Iris Bahar, Maurice Herlihy