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» The High Level Architecture for Simulations
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DATE
2009
IEEE
132views Hardware» more  DATE 2009»
16 years 1 months ago
Power and performance of read-write aware Hybrid Caches with non-volatile memories
—Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), offer dramatically different power-performance characteristics when com...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yu...
SIGMETRICS
2005
ACM
197views Hardware» more  SIGMETRICS 2005»
16 years 4 days ago
On the performance characteristics of WLANs: revisited
Wide-spread deployment of infrastructure WLANs has made Wi-Fi an integral part of today’s Internet access technology. Despite its crucial role in affecting end-to-end performan...
Sunwoong Choi, Kihong Park, Chong-kwon Kim
BROADNETS
2004
IEEE
15 years 10 months ago
DCC-MAC: A Decentralized MAC Protocol for 802.15.4a-like UWB Mobile Ad-Hoc Networks Based on Dynamic Channel Coding
We present a joint PHY/MAC architecture (DCC-MAC) for 802.15.4a-like networks based on PPM-UWB. Unlike traditional approaches it fully utilizes the specific nature of UWB to achie...
Jean-Yves Le Boudec, Ruben Merz, Bozidar Radunovic...
TC
2008
15 years 6 months ago
Exploiting In-Memory and On-Disk Redundancy to Conserve Energy in Storage Systems
Abstract--Today's storage systems place an imperative demand on energy efficiency. A storage system often places single-rotationrate disks into standby mode by stopping them f...
Jun Wang, Xiaoyu Yao, Huijun Zhu
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
15 years 4 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt