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» The High Level Architecture for Simulations
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ASPDAC
2004
ACM
89views Hardware» more  ASPDAC 2004»
15 years 10 months ago
Predictable design of low power systems by pre-implementation estimation and optimization
- Each year tens of billions of Dollars are wasted by the microelectronics industry because of missed deadlines and delayed design projects. These delays are partially due to desig...
Wolfgang Nebel
CLUSTER
2002
IEEE
15 years 6 months ago
File and Object Replication in Data Grids
Data replication is a key issue in a Data Grid and can be managed in different ways and at different levels of granularity: for example, at the file level or object level. In the ...
Heinz Stockinger, Asad Samar, Koen Holtman, Willia...
ICC
2008
IEEE
126views Communications» more  ICC 2008»
16 years 1 months ago
Backlog Aware Scheduling for Large Buffered Crossbar Switches
—A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with i...
Aditya Dua, Benjamin Yolken, Nicholas Bambos, Wlad...
ISCA
2010
IEEE
247views Hardware» more  ISCA 2010»
15 years 10 months ago
An integrated GPU power and performance model
GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Performance optimization for multi-core processors has been a c...
Sunpyo Hong, Hyesoon Kim
WSC
2007
15 years 9 months ago
An analysis of tool capabilities in the photolithography area of an ASIC fab
Photolithography is generally regarded as the most constraining element in semiconductor manufacturing. This is primarily attributable to the high capital investment and extensive...
P. J. Byrne, Cathal Heavey, Kamil Erkan Kabak