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DATE
2000
IEEE
130views Hardware» more  DATE 2000»
15 years 11 months ago
Optimal Hardware Pattern Generation for Functional BIST
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, H...
SOFTVIS
2010
ACM
15 years 6 months ago
TIE: an interactive visualization of thread interleavings
Multi-core processors have become increasingly prevalent, driving a software shift toward concurrent programs which best utilize these processors. Testing and debugging concurrent...
Gowritharan Maheswara, Jeremy S. Bradbury, Christo...
ICANN
2005
Springer
16 years 9 hour ago
Model Selection Under Covariate Shift
A common assumption in supervised learning is that the training and test input points follow the same probability distribution. However, this assumption is not fulfilled, e.g., in...
Masashi Sugiyama, Klaus-Robert Müller
VTC
2008
IEEE
16 years 26 days ago
Hardware Simulator for MIMO Radio Channels: Design and Features of the Digital Block
– This paper presents the realization of the digital block of a hardware simulator of MIMO propagation channels for UMTS and WLAN applications. The hardware simulator must reprod...
Sylvie Picol, Gheorghe Zaharia, Dominique Houzet, ...
GECCO
2005
Springer
107views Optimization» more  GECCO 2005»
16 years 13 hour ago
Exposing origin-seeking bias in PSO
We discuss testing methods for exposing origin-seeking bias in PSO motion algorithms. The strategy of resizing the initialization space, proposed by Gehlhaar and Fogel and made po...
Christopher K. Monson, Kevin D. Seppi