Sciweavers

5247 search results - page 912 / 1050
» The Generalized A* Architecture
Sort
View
VLSID
2002
IEEE
207views VLSI» more  VLSID 2002»
16 years 7 months ago
Synthesis of High Performance Low Power Dynamic CMOS Circuits
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
Debasis Samanta, Nishant Sinha, Ajit Pal
HPCA
2008
IEEE
16 years 6 months ago
Uncovering hidden loop level parallelism in sequential applications
As multicore systems become the dominant mainstream computing technology, one of the most difficult challenges the industry faces is the software. Applications with large amounts ...
Hongtao Zhong, Mojtaba Mehrara, Steven A. Lieberma...
HPCA
2003
IEEE
16 years 6 months ago
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
Increasing focus on power dissipation issues in current microprocessors has led to a host of proposals for clock gating and other power-saving techniques. While generally effectiv...
Russ Joseph, David Brooks, Margaret Martonosi
RECOMB
2008
Springer
16 years 6 months ago
BayCis: A Bayesian Hierarchical HMM for Cis-Regulatory Module Decoding in Metazoan Genomes
The transcriptional regulatory sequences in metazoan genomes often consist of multiple cis-regulatory modules (CRMs). Each CRM contains locally enriched occurrences of binding site...
Tien-ho Lin, Pradipta Ray, Geir Kjetil Sandve, Sel...
STOC
2007
ACM
142views Algorithms» more  STOC 2007»
16 years 6 months ago
Lower bounds for randomized read/write stream algorithms
Motivated by the capabilities of modern storage architectures, we consider the following generalization of the data stream model where the algorithm has sequential access to multi...
Paul Beame, T. S. Jayram, Atri Rudra