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» The Generalized A* Architecture
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160
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VLSID
2006
IEEE
121views VLSI» more  VLSID 2006»
16 years 7 months ago
An Integrated Approach for Combining BDD and SAT Provers
Many formal verification tools today are based on Boolean proof techniques. The two most powerful approaches in this context are Binary Decision Diagrams (BDDs) and methods based ...
Rolf Drechsler, Görschwin Fey, Sebastian Kind...
VLSID
2002
IEEE
94views VLSI» more  VLSID 2002»
16 years 7 months ago
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design
In floorplan design, it is common that a designer will want to control the positions of some modules in the final packing for various purposes like data path alignment, I/O connec...
Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho
184
Voted
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
16 years 7 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
161
Voted
HPCA
2005
IEEE
16 years 7 months ago
A Unified Compressed Memory Hierarchy
The memory system's large and growing contribution to system performance motivates more aggressive approaches to improving its efficiency. We propose and analyze a memory hie...
Erik G. Hallnor, Steven K. Reinhardt
HPCA
2005
IEEE
16 years 7 months ago
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors
Memory system optimizations have been well studied on single-threaded systems; however, the wide use of simultaneous multithreading (SMT) techniques raises questions over their ef...
Zhichun Zhu, Zhao Zhang