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EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
15 years 11 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
ISCA
1994
IEEE
129views Hardware» more  ISCA 1994»
15 years 11 months ago
Software Versus Hardware Shared-Memory Implementation: A Case Study
We comparethe performance of software-supported shared memory on a general-purpose network to hardware-supported shared memory on a dedicated interconnect. Up to eight processors,...
Alan L. Cox, Sandhya Dwarkadas, Peter J. Keleher, ...
ATAL
2007
Springer
15 years 10 months ago
Determining confidence when integrating contributions from multiple agents
Integrating contributions received from other agents is an essential activity in multi-agent systems (MASs). Not only must related contributions be integrated together, but the co...
Raphen Becker, Daniel D. Corkill
CF
2007
ACM
15 years 10 months ago
Accelerating memory decryption and authentication with frequent value prediction
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
Weidong Shi, Hsien-Hsin S. Lee
ACSAC
2004
IEEE
15 years 10 months ago
RACOON: Rapidly Generating User Command Data For Anomaly Detection From Customizable Templates
One of the biggest obstacles faced by user command based anomaly detection techniques is the paucity of data. Gathering command data is a slow process often spanning months or yea...
Ramkumar Chinchani, Aarthie Muthukrishnan, Madhusu...
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