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    FPL
    2009
    Springer
    166views Hardware» more  FPL 2009»
    Modeling post-techmapping and post-clustering FPGA circuit depth
    15 years 11 months ago
    Modeling post-techmapping and post-clustering FPGA circuit depth
    Download  www.cse.cuhk.edu.hk
    This paper presents an analytical model that relates FPGA architectural parameters to the expected speed of FPGA implementation. More precisely, the model relates the lookuptable ...
    Joydip Das, Steven J. E. Wilton, Philip Heng Wai L...
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    DAC
    1999
    ACM
    130views Computer Architecture» more  DAC 1999»
    A Model for Scheduling Protocol-Constrained Components and Environments
    16 years 7 months ago
    A Model for Scheduling Protocol-Constrained Components and Environments
    Download  bears.ece.ucsb.edu
    Steve Haynal, Forrest Brewer
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    DAC
    2001
    ACM
    112views Computer Architecture» more  DAC 2001»
    Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk
    16 years 7 months ago
    Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk
    Download  vada.skku.ac.kr
    Yehia Massoud, Jamil Kawa, Don MacMillen, Jacob Wh...
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    DAC
    2002
    ACM
    92views Computer Architecture» more  DAC 2002»
    A detailed cost model for concurrent use with hardware/software co-design
    16 years 7 months ago
    A detailed cost model for concurrent use with hardware/software co-design
    Download  www.enme.umd.edu
    Daniel Ragan, Peter Sandborn, Paul Stoaks
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    VLSID
    2007
    IEEE
    112views VLSI» more  VLSID 2007»
    Synthesizing "Verification Aware" Models: Why and How?
    16 years 7 months ago
    Synthesizing "Verification Aware" Models: Why and How?
    Download  www.nec-labs.com
    Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazu...
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