6834 search results - page 248 / 1367 » The Fail-Heterogeneous Architectural Model |
199
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DAC
2007
ACM
15 years 10 months ago
2007
ACM
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
179
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DAC
2004
ACM
15 years 10 months ago
2004
ACM
There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assum...
188
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DAC
2004
ACM
15 years 10 months ago
2004
ACM
The performance of timing-driven placement methods depends strongly on the choice of the net model. In this paper a more precise net model is presented that does not increase nume...
176
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
303
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AVI
2000
15 years 8 months ago
2000
Declarative models play an important role in most software design activities, by allowing designs to be constructed that selectively abstract over complex implementation details. ...