6834 search results - page 1193 / 1367 » The Fail-Heterogeneous Architectural Model |
169
click to vote
VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
171
click to vote
VLSID
2001
IEEE
16 years 6 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
183
click to vote
HPCA
2007
IEEE
16 years 6 months ago
2007
IEEE
This paper evaluates the suitability of the MapReduce model for multi-core and multi-processor systems. MapReduce was created by Google for application development on data-centers...
231
click to vote
HPCA
2003
IEEE
16 years 6 months ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
205
click to vote
SIGMOD
2003
ACM
16 years 6 months ago
2003
ACM
We consider the problem of approximating sliding window joins over data streams in a data stream processing system with limited resources. In our model, we deal with resource cons...