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VLSID
2004
IEEE
111views VLSI» more  VLSID 2004»
16 years 7 months ago
On Buffering Schemes for Long Multi-Layer Nets
We consider the problem of minimizing the delay in signal transmission over point-to-point connections across multiple metal layers in a VLSI circuit. We present an exact solution...
Vani Prasad, Madhav P. Desai
VLSID
2004
IEEE
91views VLSI» more  VLSID 2004»
16 years 7 months ago
Program Slicing for ATPG-Based Property Checking
This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (...
Vivekananda M. Vedula, Whitney J. Townsend, Jacob ...
VLSID
2004
IEEE
112views VLSI» more  VLSID 2004»
16 years 7 months ago
Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization
It has been observed that even highly optimized software programs perform "redundant" computations during their execution, due to the nature (statistics) of the values a...
Weidong Wang, Anand Raghunathan, Niraj K. Jha
VLSID
2002
IEEE
74views VLSI» more  VLSID 2002»
16 years 7 months ago
Interconnect Energy Dissipation in High-Speed ULSI Circuits
- This work presents accurate closed-form expressions for the interconnect energy dissipation in high-speed ULSI circuits. Unlike previous works, the energy is calculated using an ...
Payam Heydari, Massoud Pedram
HPCA
2008
IEEE
16 years 7 months ago
Roughness of microarchitectural design topologies and its implications for optimization
Recent advances in statistical inference and machine learning close the divide between simulation and classical optimization, thereby enabling more rigorous and robust microarchit...
Benjamin C. Lee, David M. Brooks
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