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VLSID
2007
IEEE
154views VLSI» more  VLSID 2007»
16 years 7 months ago
Model Based Test Generation for Microprocessor Architecture Validation
Functional validation of microprocessors is growing in complexity in current and future microprocessors. Traditionally, the different components (or validation collaterals) used i...
Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Di...
GECCO
2004
Springer
145views Optimization» more  GECCO 2004»
15 years 12 months ago
Search Based Automatic Test-Data Generation at an Architectural Level
Abstract. The need for effective testing techniques for architectural level descriptions is widely recognised. However, due to the variety of domain-specific architectural descript...
Yuan Zhan, John A. Clark
CBMS
2008
IEEE
15 years 8 months ago
Generating GO Slim Using Relational Database Management Systems to Support Proteomics Analysis
The Gene Ontology Consortium built the Gene Ontology database (GO) to address the need for a common standard in naming genes and gene products. Using different names for the same ...
Getiria Onsongo, Hongwei Xie, Timothy J. Griffin, ...
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
15 years 11 months ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi
FPGA
2000
ACM
177views FPGA» more  FPGA 2000»
15 years 10 months ago
Automatic generation of FPGA routing architectures from high-level descriptions
In this paper we present a "high-level" FPGA architecture description language which lets FPGA architects succinctly and quickly describe an FPGA routing architecture. W...
Vaughn Betz, Jonathan Rose