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MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
16 years 17 days ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
ATAL
2009
Springer
15 years 10 months ago
Choice, interoperability, and conformance in interaction protocols and service choreographies
Many real-world applications of multiagent systems require independently designed (heterogeneous) and operated (autonomous) agents to interoperate. We consider agents who offer bu...
Matteo Baldoni, Cristina Baroglio, Amit K. Chopra,...
DAC
2009
ACM
16 years 7 months ago
Context-sensitive timing analysis of Esterel programs
Traditionally, synchronous languages, such as Esterel, have been compiled into hardware, where timing analysis is relatively easy. When compiled into software ? e.g., into sequent...
Lei Ju, Bach Khoa Huynh, Samarjit Chakraborty, Abh...
WWW
2006
ACM
16 years 7 months ago
Interactive wrapper generation with minimal user effort
While much of the data on the web is unstructured in nature, there is also a significant amount of embedded structured data, such as product information on e-commerce sites or sto...
Utku Irmak, Torsten Suel
CASES
2006
ACM
16 years 16 days ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh