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DAC
2005
ACM
16 years 7 months ago
High performance encryption cores for 3G networks
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
René Cumplido, Tomás Balderas-Contre...
ISSS
1996
IEEE
125views Hardware» more  ISSS 1996»
15 years 11 months ago
Size-Constrained Code Placement for Cache Miss Rate Reduction
In design of an embedded system with a cache, it is important to minimize the cache miss rate to reduce the power consumption as well as to improvethe performance of the system. W...
Hiroyuki Tomiyama, Hiroto Yasuura
CODES
2004
IEEE
15 years 10 months ago
Power-aware communication optimization for networks-on-chips with voltage scalable links
Networks-on-Chip (NoC) is emerging as a practical development platform for future systems-on-chip products. We propose an energyefficient static algorithm which optimizes the ener...
Dongkun Shin, Jihong Kim
ISOLA
2010
Springer
15 years 5 months ago
An Interface Algebra for Estimating Worst-Case Traversal Times in Component Networks
Abstract. Interface-based design relies on the idea that different components of a system may be developed independently and a system designer can connect them together only if th...
Nikolay Stoimenov, Samarjit Chakraborty, Lothar Th...
IWC
2007
134views more  IWC 2007»
15 years 6 months ago
Disrupting digital library development with scenario informed design
In recent years, there has been great interest in scenario-based design and other forms of user-centred design. However, there are many design processes that, often for good reaso...
Ann Blandford, Suzette Keith, Richard Butterworth,...