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CODES
2008
IEEE
16 years 1 months ago
Intra- and inter-processor hybrid performance modeling for MPSoC architectures
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid perfor...
Frank E. B. Ophelders, Samarjit Chakraborty, Henk ...
151
Voted
DATE
2008
IEEE
102views Hardware» more  DATE 2008»
16 years 1 months ago
Vectorization of Reed Solomon Decoding and Mapping on the EVP
Reed Solomon (RS) codes are used in a variety of (wireless) communication systems. Although commonly implemented in dedicated hardware, this paper explores the mapping of high-thr...
Akash Kumar, Kees van Berkel
ECRTS
2007
IEEE
15 years 10 months ago
The Space of EDF Feasible Deadlines
It is well known that the performance of computer controlled systems is heavily affected by delays and jitter occurring in the control loops, which are mainly caused by the interf...
Enrico Bini, Giorgio C. Buttazzo
ATVA
2006
Springer
206views Hardware» more  ATVA 2006»
15 years 10 months ago
Compositional Reasoning for Hardware/Software Co-verification
In this paper, we present and illustrate an approach to compositional reasoning for hardware/software co-verification of embedded systems. The major challenges in compositional rea...
Fei Xie, Guowu Yang, Xiaoyu Song
172
Voted
ISCA
2006
IEEE
162views Hardware» more  ISCA 2006»
16 years 23 days ago
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
Feihui Li, Chrysostomos Nicopoulos, Thomas D. Rich...