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IPPS
2006
IEEE
16 years 16 days ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
PARELEC
2006
IEEE
16 years 15 days ago
Application-Driven Development of Concurrent Packet Processing Platforms
We have developed an application-driven methodology for implementing parallel and heterogeneous programmable platforms. We deploy our flow for network access platforms where we h...
Christian Sauer, Matthias Gries, Jörg-Christi...
PARELEC
2006
IEEE
16 years 15 days ago
Hierarchical Partitioning for Piecewise Linear Algorithms
processor arrays can be used as accelerators for a plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor arr...
Hritam Dutta, Frank Hannig, Jürgen Teich
SIBGRAPI
2006
IEEE
16 years 15 days ago
Improving 2D mesh image segmentation with Markovian Random Fields
Traditional mesh segmentation methods normally operate on geometrical models with no image information. On the other hand, 2D image-based mesh generation and segmentation counterp...
Alex Jesus Cuadros-Vargas, Leandro C. Gerhardinger...
ACCV
2006
Springer
16 years 15 days ago
Vision-Based Posing of 3D Virtual Actors
Construction of key poses is one of the most tedious and time consuming steps in synthesizing of 3D virtual actors. Recent alternate schemes expect the user to specify two inputs. ...
Ameya S. Vaidya, Appu Shaji, Sharat Chandran