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CGO
2005
IEEE
16 years 7 days ago
Maintaining Consistency and Bounding Capacity of Software Code Caches
Software code caches are becoming ubiquitous, in dynamic optimizers, runtime tool platforms, dynamic translators, fast simulators and emulators, and dynamic compilers. Caching fre...
Derek Bruening, Saman P. Amarasinghe
ACMSE
2004
ACM
16 years 1 days ago
Execution characteristics of SPEC CPU2000 benchmarks: Intel C++ vs. Microsoft VC++
Modern processors include features such as deep pipelining, multilevel cache hierarchy, branch predictors, out of order execution engine, and advanced floating point and multimedi...
Swathi Tanjore Gurumani, Aleksandar Milenkovic
MICRO
2003
IEEE
258views Hardware» more  MICRO 2003»
15 years 12 months ago
LLVA: A Low-level Virtual Instruction Set Architecture
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
Vikram S. Adve, Chris Lattner, Michael Brukman, An...
ICS
2003
Tsinghua U.
15 years 11 months ago
Estimating cache misses and locality using stack distances
Cache behavior modeling is an important part of modern optimizing compilers. In this paper we present a method to estimate the number of cache misses, at compile time, using a mac...
Calin Cascaval, David A. Padua
SIGGRAPH
2010
ACM
15 years 11 months ago
Paneling architectural freeform surfaces
The emergence of large-scale freeform shapes in architecture poses big challenges to the fabrication of such structures. A key problem is the approximation of the design surface b...
Michael Eigensatz, Martin Kilian, Alexander Schift...