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ISCA
2002
IEEE
102views Hardware» more  ISCA 2002»
15 years 11 months ago
Implementing Optimizations at Decode Time
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
Ilhyun Kim, Mikko H. Lipasti
MICRO
2002
IEEE
113views Hardware» more  MICRO 2002»
15 years 11 months ago
Vacuum packing: extracting hardware-detected program phases for post-link optimization
This paper presents Vacuum Packing, a new approach to profile-based program optimization. Instead of using traditional aggregate or summarized execution profile weights, this ap...
Ronald D. Barnes, Erik M. Nystrom, Matthew C. Mert...
WCRE
2002
IEEE
15 years 11 months ago
Register Liveness Analysis for Optimizing Dynamic Binary Translation
Dynamic binary translators compile machine code from a source architecture to a target architecture at run time. Due to the hard time constraints of just-in-time compilation only ...
Mark Probst, Andreas Krall, Bernhard Scholz
ICRA
2000
IEEE
130views Robotics» more  ICRA 2000»
15 years 11 months ago
Design and Actuation Optimization of a 4 Axes Biped Robot for Walking and Running
Several french laboratories, joint in the CNRS Project "Control of Legged Robots", have defined a biped robot intented to experiment walking and running gaits. This bipe...
Cambrini Chevallereau, Philippe Sardain
SIGGRAPH
1999
ACM
15 years 11 months ago
Optimization of Mesh Locality for Transparent Vertex Caching
Bus traffic between the graphics subsystem and memory can become a bottleneck when rendering geometrically complex meshes. In this paper, we investigate the use of vertex caching...
Hugues Hoppe