2155 search results - page 262 / 431 » The EM-X Parallel Computer: Architecture and Basic Performan... |
166
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HPCA
2004
IEEE
16 years 6 months ago
2004
IEEE
Design of wakeup-free issue queues is becoming desirable due to the increasing complexity associated with broadcast-based instruction wakeup. The effectiveness of most wakeup-free...
202
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ANCS
2009
ACM
15 years 4 months ago
2009
ACM
In this paper, we propose an extensible Open-Architecture Services platform (OASis) for high-performance network processing. OASis embraces recent advances of open technologies, i...
167
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ICDCS
2000
IEEE
15 years 10 months ago
2000
IEEE
1 Switched system-area networks enable thousands of storage devices to be shared and directly accessed by end hosts, promising databases and filesystems highly scalable, reliable ...
175
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IEEEPACT
1999
IEEE
15 years 10 months ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...
180
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PPOPP
1993
ACM
15 years 10 months ago
1993
ACM
This paper discusses some of the issues involved in implementing a shared-address space programming model on large-scale, distributed-memory multiprocessors. While such a programm...