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HPCA
2003
IEEE
16 years 6 months ago
Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors
Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or specul...
María Jesús Garzarán, Milos P...
IEEEPACT
2002
IEEE
15 years 11 months ago
Using the Compiler to Improve Cache Replacement Decisions
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with L...
Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosen...
HPDC
2008
IEEE
15 years 6 months ago
Eliminating the middleman: peer-to-peer dataflow
Efficiently executing large-scale, data-intensive workflows such as Montage must take into account the volume and pattern of communication. When orchestrating data-centric workflo...
Adam Barker, Jon B. Weissman, Jano I. van Hemert
PACT
2007
Springer
16 years 17 days ago
Support for Fine-Grained Synchronization in Shared-Memory Multiprocessors
Abstract. It has been already verified that hardware-supported finegrain synchronization provides a significant performance improvement over coarse-grained synchronization mecha...
Vladimir Vlassov, Oscar Sierra Merino, Csaba Andra...
IPPS
1998
IEEE
15 years 10 months ago
SIMD and Mixed-Mode Implementations of a Visual Tracking Algorithm
This paper describes the implementation of a featurebased visual tracking algorithm on a SIMD MasPar MP-1 and the mixed-mode PASM prototype. The sequential algorithm is introduced...
Mark Bernd Kulaczewski, Howard Jay Siegel