2155 search results - page 240 / 431 » The EM-X Parallel Computer: Architecture and Basic Performan... |
188
click to vote
HOTI
2005
IEEE
16 years 2 days ago
2005
IEEE
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
157
click to vote
ARC
2008
Springer
15 years 8 months ago
2008
Springer
Abstract. Loops are an important source of optimization. In this paper, we address such optimizations for those cases when loops contain kernels mapped on reconfigurable fabric. We...
162
click to vote
ASPLOS
1989
ACM
15 years 10 months ago
1989
ACM
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
190
click to vote
MICCAI
2002
Springer
16 years 7 months ago
2002
Springer
Abstract. High performance computing has become a key step to introduce computer tools, like real-time registration, in the medical field. To achieve real-time processing, one usua...
180
click to vote
PDP
2011
IEEE
14 years 10 months ago
2011
IEEE
—This paper proposes a parallelization scheme for parameter sweep (PS) applications using the compute unified device architecture (CUDA). Our scheme focuses on PS applications w...