2155 search results - page 236 / 431 » The EM-X Parallel Computer: Architecture and Basic Performan... |
154
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APCSAC
2003
IEEE
15 years 10 months ago
2003
IEEE
Very Long Instruction Word (VLIW) architectures exploit instruction level parallelism (ILP) with the help of the compiler to achieve higher instruction throughput with minimal hard...
152
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DAC
1996
ACM
15 years 10 months ago
1996
ACM
PPP is a Web-based simulation and synthesis environment for low-power design. In this paper we describe the gate-level simulation engine of PPP, that achieves accuracy always with...
179
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ICS
1999
Tsinghua U.
15 years 10 months ago
1999
Tsinghua U.
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
167
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CHI
2007
ACM
16 years 6 months ago
2007
ACM
The design of applications using mobile devices needs a different quality assessment than those known for desktop applications. Of the many aspects that have to be taken into acco...
193
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HIPC
2007
Springer
16 years 20 days ago
2007
Springer
Molecular dynamics simulations are a common and often repeated task in molecular biology. The need for speeding up this treatment comes from the requirement for large system simula...