2155 search results - page 202 / 431 » The EM-X Parallel Computer: Architecture and Basic Performan... |
196
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WMPI
2004
ACM
15 years 12 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
168
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MSS
2003
IEEE
15 years 11 months ago
2003
IEEE
: Several solutions have been developed to provide dataintensive applications with the highest possible data rates. Such solutions tried to utilize the available network resources ...
351
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FCCM
2011
IEEE
14 years 10 months ago
2011
IEEE
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
172
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HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementatio...
160
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed a...