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HOTI
2005
IEEE
16 years 5 days ago
Design of Randomized Multichannel Packet Storage for High Performance Routers
High performance routers require substantial amounts of memory to store packets awaiting transmission, requiring the use of dedicated memory devices with the density and capacity ...
Sailesh Kumar, Patrick Crowley, Jonathan S. Turner
JPDC
2008
167views more  JPDC 2008»
15 years 6 months ago
A performance study of general-purpose applications on graphics processors using CUDA
Graphics processors (GPUs) provide a vast number of simple, data-parallel, deeply multithreaded cores and high memory bandwidths. GPU architectures are becoming increasingly progr...
Shuai Che, Michael Boyer, Jiayuan Meng, David Tarj...
VLSISP
1998
128views more  VLSISP 1998»
15 years 6 months ago
A Low Power DSP Engine for Wireless Communications
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
Ingrid Verbauwhede, Mihran Touriguian
DAC
2007
ACM
16 years 7 months ago
Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors
Three-Dimensional integration provides a simultaneous improvement in wire-related delay and power consumption of microprocessor circuits. Prior work has looked at the performance,...
Kiran Puttaswamy, Gabriel H. Loh
EDOC
2003
IEEE
15 years 12 months ago
Contract Performance Assessment for Secure and Dynamic Virtual Collaborations
In this paper we sketch a framework supporting contract enactment within the context of virtual organisation units that are dynamically created in order to achieve a common object...
Theodosis Dimitrakos, Ivan Djordjevic, Zoran Milos...