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IEEEPACT
2009
IEEE
16 years 1 months ago
Interprocedural Load Elimination for Dynamic Optimization of Parallel Programs
Abstract—Load elimination is a classical compiler transformation that is increasing in importance for multi-core and many-core architectures. The effect of the transformation is ...
Rajkishore Barik, Vivek Sarkar
CCGRID
2001
IEEE
15 years 10 months ago
QoS-Aware Discovery of Wide-Area Distributed Services
The global computational grids bring together distributed computation/communication resources. Beyond this, we envision the emergence of global `service grids', which provide...
Dongyan Xu, Klara Nahrstedt, Duangdao Wichadakul
DAC
2002
ACM
16 years 7 months ago
An energy saving strategy based on adaptive loop parallelization
In this paper, we evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using different number of processors if doing so is be...
Ismail Kadayif, Mahmut T. Kandemir, Mustafa Karak&...
HPDC
2007
IEEE
16 years 27 days ago
An architecture for virtual organization (VO)-based effective peering of content delivery networks
The proprietary nature of existing Content Delivery Networks (CDNs) means they are closed and do not naturally cooperate, resulting in “islands” of CDNs. Finding ways for dist...
Al-Mukaddim Khan Pathan, James Broberg, Kris Buben...
ICPP
1993
IEEE
15 years 10 months ago
Dependence Analysis and Architecture Design for Bit-Level Algorithms
:. In designing application-specific bit-level architectures and in programming existing bit-level processor arrays, it is necessary to expand a word-level algorithm into its bit-...
Weijia Shang, Benjamin W. Wah