2155 search results - page 180 / 431 » The EM-X Parallel Computer: Architecture and Basic Performan... |
158
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IEEEPACT
2008
IEEE
16 years 29 days ago
2008
IEEE
This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Prev...
162
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IPPS
2005
IEEE
16 years 4 days ago
2005
IEEE
Soft-core processors exploit the flexibility of Field Programmable Gate Arrays (FPGAs) to allow a system designer to customize the processor to the needs of a target application....
172
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HPDC
1999
IEEE
15 years 11 months ago
1999
IEEE
This paper reports on the architecture and design of Starfish, an environment for executing dynamic (and static) MPI-2 programs on a cluster of workstations. Starfish is unique in ...
153
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ICPP
1991
IEEE
15 years 10 months ago
1991
IEEE
This paper presents an architecture for programmable systolic arrays that provides simple and e cient systolic communication. The Brown Systolic Array is a linear implementation o...
152
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VLSID
2007
IEEE
16 years 7 months ago
2007
IEEE
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...