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ASAP
2008
IEEE
146views Hardware» more  ASAP 2008»
16 years 1 months ago
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...
Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary...
BMVC
2000
15 years 8 months ago
A New Approach for Vanishing Point Detection in Architectural Environments
A man-made environment is characterized by a lot of parallel lines and a lot of orthogonal edges. In this article, a new method for detecting the three mutual orthogonal direction...
Carsten Rother
IPPS
2010
IEEE
15 years 4 months ago
Structuring the execution of OpenMP applications for multicore architectures
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
François Broquedis, Olivier Aumage, Brice G...
HPCA
2006
IEEE
16 years 7 months ago
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
TVLSI
2008
90views more  TVLSI 2008»
15 years 6 months ago
A Special-Purpose Architecture for Solving the Breakpoint Median Problem
Abstract--In this paper, we describe the design for a co-processor for whole-genome phylogenetic reconstruction. Our current design performs a parallelized breakpoint median comput...
Jason D. Bakos, Panormitis E. Elenis